1. Field of the Invention
The present invention relates to a method of manufacturing a read only memory (ROM) device of a semiconductor device. More particularly, the present invention relates to a method of manufacturing a NOR-type mask ROM device and a semiconductor device including the same.
2. Description of the Related Art
A ROM is a nonvolatile memory device, in which stored data is not written over during normal operation. The ROM can be classified into a mask ROM, a programmable ROM (PROM), a one time PROM (OTPROM), an erasable PROM (EPROM), and an electrically erasable PROM (EEPROM).
Data is stored in the mask ROM when it is manufactured by coding using a mask on which data intended to be stored is written. Data that has been stored in the mask ROM cannot be written over, but can be read.
Data can be coded in the mask ROM by implanting impurities into a predetermined transistor such that the predetermined transistor has a different conductivity from other transistors of the mask ROM.
Typically, when verification of a user data code is completed in a product-developing step of semiconductor devices, chip customers order a large quantity of products for each code from chip manufacturers. In order to meet the customers' demand rapidly, chip manufacturers manufacture a master version of each product beforehand and have the master version on stand-by in a bank step, i.e., a step prior to a coding step.
Here, the competitiveness of the chip manufacturers depends on turn-around time (TAT), which is the time needed to manufacture a wafer and provide a chip to a customer after acquiring a user code.
A cell of a mask ROM can be categorized into a NOR or NAND type. A NAND-type mask ROM device requires coding before a gate electrode of a transistor is formed, thus resulting in a large TAT. That is, in a NAND-type mask ROM device, before forming a gate electrode of a transistor, a photolithography process is performed to implant impurities that have the same conductivity type as a source/drain region of the transistor into a coding region of the mask ROM. Thus, a depletion-type transistor for an ON cell is completed. An OFF cell includes a transistor that has a threshold voltage Vth, which varies according to a dopant concentration of a substrate, the thickness of a gate oxide layer, and the concentration of subsequently implanted impurities in the source/drain region. Therefore, since coding of the NAND-type mask ROM is subsequently followed by formation of a gate electrode, the TAT increases.
However, in a NOR-type mask ROM, after forming a gate electrode and implanting impurities in a source/drain region of a transistor, a photolithography process is performed to implant impurities that have an opposite conductivity type to the conductivity type of the source/drain region into a coding region of the mask ROM. Thus, an OFF cell is formed by increasing the threshold voltage Vth of the coded transistor. An ON cell is a cell that has a normal threshold voltage Vth. As described above, the NOR-type mask ROM entails coding after forming the gate electrode of the transistor. Since a master wafer is on stand-by before a back end metallization, TAT can be reduced. However, the manufacturing of the NOR-type mask ROM is costly because coding after gate electrode formation requires additional reticles.